The present invention relates to a system and method for operation verification of a semiconductor integrated circuit.
To achieve the higher integration and higher-speed operation of a semiconductor integrated circuit device, the operation verification of a semiconductor integrated circuit has been performed by using a circuit simulator in the recent chip-level design of the semiconductor integrated circuit. In this case, the chip-level operation verification of the circuit is performed as follows. First, circuit simulation on a logic-cell level is performed by using a net list and then a delay library necessary for the chip-level operation verification of the circuit is produced by using the result of the circuit simulation.
The delay library shows signal propagation delays between input signals to various circuit cells and output signals therefrom. The checking of whether or not final delay values in the circuit on the chip level satisfy design values using a large number of various delay libraries ensures the chip-level operation of the semiconductor integrated circuit.
In general, a delay library is generated from the design layout of circuit cells through the following procedure in two steps.
In the first step, netlist conversion is performed by using a netlister and by using design layout information 101 for circuit cells as an input to produce a net list as connection information between elements (transistors and the like). The netlister is a software program for calculating layout parameters which describes a procedure for causing a computer to read the layout parameters and produce a net list. The netlister detects, e.g., dimensional parameters representing a configuration, such as a gate length and a gate width, circuit connection information, a resistance, and a capacitance from the design layout information for circuit cells and causes the computer to describe such information in the net list.
Next, in the second step, circuit simulation is performed by using a circuit simulator and by using the net list outputted from the netlister as an input and then operation verification for a leakage current, a delay time, and the like is performed so that a characteristic library is produced.
As semiconductor integrated circuit devices have been further miniaturized in recent years, various factors including an optical proximity effect during exposure and the local effect of a dry etching process have caused size nonuniformity during processing. As a result, an error occurs between a final configuration and a layout configuration at design stage and the problem is encountered that a delay library has not described the characteristics of actually finished circuit cells with high precision.
To solve the problem, a method has been proposed which predicts a final layout configuration from the design layout configuration of circuit cells by considering an optical proximity effect during exposure, performs circuit simulation by using the predicted final layout configuration, and thereby produces a delay library (see, e.g., Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-203907 (ABSTRACT)).
Referring to FIG. 5, a conventional method for producing a characteristic library by considering an optical proximity effect during exposure will be described herein below. FIG. 5 is a block diagram for illustrating the conventional method for operation verification of a semiconductor integrated circuit, which is disclosed in Patent Document 1.
In a first step, an OPC (Optical Proximity Correction) process for considering the optical proximity effect on the circuit-cell design layout configuration is performed first by using final layout predicting means 102 and by using circuit-cell design layout information 101 as an input to produce predicted final layout information 103 having a post-manufacturing layout configuration.
Next, in a second step, netlist conversion is performed by using a netlister 104 and by using the predicted final layout information 103 outputted from the final layout predicting means 102 as an input to produce a net list 105 as connection information between elements and the like. The netlister 104 extracts dimensional parameters representing a configuration, such as a gate length and a gate width, circuit connection information, a resistance, and a capacitance from the predicted final layout information 103 for the circuit and describes them in the net list 105.
Next, in a third step, operation verification is performed by circuit simulation using a circuit simulator 106 and using the net list 105 extracted from the netlister 104 as an input to determine a leakage current, a delay time, and the like, thereby producing a characteristic library 107 containing these items of information.
In accordance with the method disclosed in Patent Document 1, characteristics considering the optical proximity effect during exposure are described in the characteristic library 107 since circuit simulation is performed by using the net list 104 produced by using the predicted final layout information 103 to which the OPC process has been performed.
However, a conventional method for operation verification considering an optical proximity effect as described above has the following drawbacks.
First, when the OPC process for correcting the optical proximity effect is performed by using the final layout predicting means 102 with respect to the circuit-cell design layout information 101 in the first step, the configuration of the predicted final layout information 103 becomes complicated.
Then, in the second step, the dimensional parameters (the physical values of an element such as a gate length) to be used for circuit simulation are calculated by using the netlister 104 and by using the predicted final layout information 103 as an input, whereby the net list 105 storing information related to the dimensional parameters is produced. Accordingly, a sequential set of dimensional parameters are described in the net list 105.
The configuration predicted with the predicted final layout information 103 is mostly complicated. However, performing operation verification by circuit simulation in which the dimensional parameters are exactly described in conformity with the complicated configuration by using a circuit simulator is unrealistic since it involves an enormous amount of calculation.
Therefore, it is inevitable to perform circuit simulation using a simplified set of dimensional parameters.
As a result, the conventional method has the problem that, even though delay calculation is performed and a characteristic such as power consumption during standby is verified by using the circuit simulator 106, operation verification cannot provide a high-precision result.